The present invention relates to a method for manufacturing a semiconductor device.
A typical semiconductor memory device is constructed of a plurality of unit cells, each including one capacitor and one transistor. The capacitor is used to temporarily store data. The transistor is used to transfer data between a bit line and the capacitor according to a control signal. The transistor uses the characteristics of a semiconductor to change an electric conductivity according to an environment. The transistor is composed of three regions including a gate, a source, and a drain. Charge transfer occurs between the source and the drain according to a control signal input to the gate. The charge transfer between the source and the drain is achieved through a channel region using the characteristics of the semiconductor.
After a transistor gate is formed on a semiconductor substrate, impurities are doped in both sides of the gate to form a source and a drain. As a data storage capacity of the semiconductor memory device is increased and the semiconductor memory device becomes highly integrated, there is a need to reduce the unit cell size. Namely, since a design rule of the capacitor and the transistor included in the unit cell is decreased, and accordingly a channel length of a cell transistor is gradually reduced, a short channel effect and Drain Induced Barrier Lower (DIBL) occurs in a transistor deteriorates an operation reliability. Phenomena occurring due to a reduction in channel length can be solved upon maintaining a threshold voltage so that the cell transistor may perform a normal operation. In general, the shorter the transistor channel length, the larger the doping density needed in a channel formation region.
However, when the design rule is reduced to less than 100 nm, a doping density of impurities in a channel formation region is increased accordingly. This increases an electric field in a storage node (SN) junction to thereby deteriorate a refresh characteristic of the semiconductor memory device. To solve the problem, a cell transistor having 3 dimensional channel structure is used in which a channel is also formed in a vertical direction so that a channel length of a transistor can be maintained in spite of a reduction in the design rule. Namely, although a channel width in a vertical direction is short, the doping density can be reduced so long as a channel length in the vertical direction is secured, thereby preventing the refresh characteristic from being deteriorated.
In addition, the higher integration of a semiconductor device, the shorter a distance between a word line and a bit line connected to a cell transistor. Due to this, parasitic capacitance is increased to impose a limitation on an operation margin of a sense amplifier amplifying data transferred through the bit line. This deteriorates operation reliability of a semiconductor device. To solve such a problem, a buried word line structure has been proposed to reduce parasitic capacitance between a bit line and a word line. In this case, in the buried word line structure, the word line is formed only in a recess and not on an upper portion of a semiconductor substrate. In the buried word line structure, a conductive material is formed in the recess formed in the semiconductor substrate, and an upper portion of the conductive material is covered with an insulating layer to bury the word line in the semiconductor substrate. Accordingly, an electric isolation with the bit line or a contact on the semiconductor substrate on which source/drain are disposed can be clearly achieved.
As described above, after a buried word line (buried gate), a is capping insulating layer is formed to protect an electrode gate. However, in order to form a contact during a subsequent procedure, the capping insulating layer is significantly etched by mis-alignment or over-etching during an etch process to cause a short to occur between the buried word line and the contact.